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Author SHA1 Message Date
Ahmet Inan
53d1a10eeb removed AVX-512 instructions from AVX2 wrapper 2019-02-05 11:32:06 +01:00
Ahmet Inan
67949bcb76 renamed some variables and improved status output 2018-12-19 09:52:24 +01:00
Ahmet Inan
b41799c84d added LDPC decoder version with fully computed LUT 2018-12-16 09:42:02 +01:00
Ahmet Inan
e06c954148 pre-calculate R entries from directly computed first q entries 2018-12-15 22:19:52 +01:00
Ahmet Inan
6af9798553 calculate first q entries directly 2018-12-15 19:42:58 +01:00
Ahmet Inan
86bf81dd2d got rid of some modulo operations 2018-12-15 17:09:03 +01:00
Ahmet Inan
4e39392acf only need first q entries 2018-12-15 15:05:19 +01:00
Ahmet Inan
ce9674883c flattened first parity handling 2018-12-15 12:12:56 +01:00
Ahmet Inan
584f6c0d9d use max value for fake parity bit to stay on the safe side 2018-12-14 20:42:25 +01:00
Ahmet Inan
5c77e514ae added DVB T2 table B.7 2018-12-13 13:23:50 +01:00
Ahmet Inan
3060e82da6 got rid of exclusive_reduce 2018-12-13 13:23:41 +01:00
Ahmet Inan
3e881ce049 accelerate decoder using SIMD 
Also added a fake parity bit to reduce code duplication.
The fake parity bit seems not to affect the decoding performance.
 2018-12-13 11:21:58 +01:00
Ahmet Inan
199a988def added LDPC encoder and layered decoder 
lifted from my LDPC project:
https://github.com/xdsopl/LDPC
 2018-12-13 11:19:31 +01:00
Ahmet Inan
e51425e121 added vclamp() 2018-12-13 11:19:31 +01:00
Ahmet Inan
09945a18b5 added example how to test with a cross-compiler 2018-12-12 12:13:58 +01:00
Ahmet Inan
bede1046d6 redirect stdout to /dev/null 2018-12-12 12:13:58 +01:00
Ahmet Inan
72d7c6d57f added vclez() 2018-12-12 12:13:58 +01:00
Ahmet Inan
4a3d113433 fixed copy / paste error 2018-12-12 12:13:58 +01:00
Ahmet Inan
4f11a22311 added SIMD wrappers for ARM NEON, Intel SSE4.1 and AVX2 2018-12-11 09:05:12 +01:00
Ahmet Inan
bd202fa2f7 added DVB-S2X FULL BCH(32767, 32587) T=12 2018-10-29 10:07:28 +01:00
Ahmet Inan
3092fa68ee fixed compilation for g++ and stay c++11 compatible 2018-10-25 08:37:52 +02:00
Ahmet Inan
eabdff7209 added exclusive reduce algorithm 2018-10-13 10:34:42 +02:00
Ahmet Inan
80784388b6 added DVB-S2 FULL BCH(16383, 16215) T=12 2018-09-30 20:26:47 +02:00
Ahmet Inan
b75f73f5ed make sure POLY doesn't create a shorter sequence 2018-09-29 23:04:19 +02:00
Ahmet Inan
4b0a694beb split Artin Schreier imap generation code out 2018-09-29 21:24:00 +02:00
Ahmet Inan
346a4a6d08 broke the long list of minpolys 2018-09-29 11:43:24 +02:00
Ahmet Inan
24b4212271 added regression testing for BCH with packed bits 2018-09-28 13:27:59 +02:00
Ahmet Inan
691b6b6647 another nice catch by regression testing :D 2018-09-28 13:24:19 +02:00
Ahmet Inan
bc535c6d04 make sure that we always cause maximum damage 2018-09-28 12:20:23 +02:00
Ahmet Inan
02a0c4269f added regression test for the BCH reference 2018-09-28 11:01:53 +02:00
Ahmet Inan
2ae6aa734c nice catch by the regression test :) 2018-09-28 10:57:17 +02:00
Ahmet Inan
f912be0335 use constants to avoid mistakes 2018-09-28 10:09:18 +02:00
Ahmet Inan
5719ff8560 more flexible to pass the instances to the test function 2018-09-28 09:44:59 +02:00
Ahmet Inan
903bf07584 added typedef to shorten the random generator lines 2018-09-28 09:06:29 +02:00
Ahmet Inan
ab44dc4042 return -1 if location is before data 2018-09-28 08:44:45 +02:00
Ahmet Inan
e660ae8c39 added regression test for RS 2018-09-28 08:02:11 +02:00
Ahmet Inan
62819a5376 added data_len argument for shortened codes 2018-09-27 18:29:13 +02:00
Ahmet Inan
f545b5d6ab handle data and parity seperate in both BCH and RS 2018-09-27 13:55:54 +02:00
Ahmet Inan
6b3bc5e534 added update_syndromes() helper 2018-09-27 10:33:47 +02:00
Ahmet Inan
8268ba3f85 moved code[j] out of the inner loop 2018-09-27 10:22:27 +02:00
Ahmet Inan
d504673812 added slb1() to clean up the mess 2018-09-24 12:25:25 +02:00
Ahmet Inan
c133ab2553 merge generator xor with shifting 2018-09-24 11:56:42 +02:00
Ahmet Inan
73e475ba76 align generator with parity bits to xor bytewise 2018-09-24 11:44:02 +02:00
Ahmet Inan
ca24063591 shift first then xor with generator 2018-09-24 10:54:26 +02:00
Ahmet Inan
c90e9a6a23 zero out parity bits bytewise 2018-09-23 21:40:56 +02:00
Ahmet Inan
e62dbb13c7 reverse generator order to match order of message 2018-09-23 21:37:46 +02:00
Ahmet Inan
4b7006651e also speed up the shifting of the mixed byte 2018-09-23 17:13:05 +02:00
Ahmet Inan
cfffac5010 speed up the shift a bit 2018-09-23 11:32:41 +02:00
Ahmet Inan
661f69efae test if minpoly is bigger than zero 2018-09-23 10:14:47 +02:00
Ahmet Inan
42ff499e23 use value_type 2018-09-22 19:56:52 +02:00