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added SIMD wrappers for ARM NEON, Intel SSE4.1 and AVX2
This commit is contained in:
Ahmet Inan
parent
bd202fa2f7
commit
4f11a22311
5 changed files with 4004 additions and 0 deletions
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@ -65,3 +65,10 @@ It computes the following, but having only O(N) complexity and using O(1) extra
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output[i] = op(output[i], input[j]);
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```
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### [simd.hh](simd.hh)
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Single instruction, multiple data ([SIMD](https://en.wikipedia.org/wiki/SIMD)) wrappers for:
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* [ARM NEON](https://en.wikipedia.org/wiki/ARM_architecture#Advanced_SIMD_(NEON)) ([neon.hh](neon.hh))
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* [Intel SSE4.1](https://en.wikipedia.org/wiki/SSE4) ([sse4_1.hh](sse4_1.hh))
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* [Intel AVX2](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions) ([avx2.hh](avx2.hh))
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990
avx2.hh
Normal file
990
avx2.hh
Normal file
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@ -0,0 +1,990 @@
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/*
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Intel AVX2 acceleration
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Copyright 2018 Ahmet Inan <inan@aicodix.de>
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*/
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#ifndef AVX2_HH
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#define AVX2_HH
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#include <immintrin.h>
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template <>
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union SIMD<float, 8>
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{
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static const int SIZE = 8;
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typedef float value_type;
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typedef uint32_t uint_type;
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__m256 m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<double, 4>
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{
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static const int SIZE = 4;
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typedef double value_type;
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typedef uint64_t uint_type;
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__m256d m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<int8_t, 32>
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{
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static const int SIZE = 32;
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typedef int8_t value_type;
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typedef uint8_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<int16_t, 16>
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{
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static const int SIZE = 16;
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typedef int16_t value_type;
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typedef uint16_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<int32_t, 8>
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{
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static const int SIZE = 8;
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typedef int32_t value_type;
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typedef uint32_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<int64_t, 4>
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{
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static const int SIZE = 4;
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typedef int64_t value_type;
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typedef uint64_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<uint8_t, 32>
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{
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static const int SIZE = 32;
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typedef uint8_t value_type;
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typedef uint8_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<uint16_t, 16>
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{
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static const int SIZE = 16;
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typedef uint16_t value_type;
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typedef uint16_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<uint32_t, 8>
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{
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static const int SIZE = 8;
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typedef uint32_t value_type;
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typedef uint32_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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union SIMD<uint64_t, 4>
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{
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static const int SIZE = 4;
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typedef uint64_t value_type;
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typedef uint64_t uint_type;
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__m256i m;
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value_type v[SIZE];
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uint_type u[SIZE];
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};
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template <>
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inline SIMD<float, 8> vreinterpret(SIMD<uint32_t, 8> a)
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{
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SIMD<float, 8> tmp;
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tmp.m = (__m256)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint32_t, 8> vreinterpret(SIMD<float, 8> a)
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{
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SIMD<uint32_t, 8> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vreinterpret(SIMD<uint64_t, 4> a)
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{
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SIMD<double, 4> tmp;
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tmp.m = (__m256d)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint64_t, 4> vreinterpret(SIMD<double, 4> a)
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{
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SIMD<uint64_t, 4> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint8_t, 32> vreinterpret(SIMD<int8_t, 32> a)
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{
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SIMD<uint8_t, 32> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vreinterpret(SIMD<uint8_t, 32> a)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint16_t, 16> vreinterpret(SIMD<int16_t, 16> a)
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{
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SIMD<uint16_t, 16> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vreinterpret(SIMD<uint16_t, 16> a)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint32_t, 8> vreinterpret(SIMD<int32_t, 8> a)
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{
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SIMD<uint32_t, 8> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<int32_t, 8> vreinterpret(SIMD<uint32_t, 8> a)
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{
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SIMD<int32_t, 8> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<uint64_t, 4> vreinterpret(SIMD<int64_t, 4> a)
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{
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SIMD<uint64_t, 4> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<int64_t, 4> vreinterpret(SIMD<uint64_t, 4> a)
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{
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SIMD<int64_t, 4> tmp;
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tmp.m = (__m256i)a.m;
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return tmp;
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}
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template <>
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inline SIMD<float, 8> vdup<SIMD<float, 8>>(float a)
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{
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SIMD<float, 8> tmp;
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tmp.m = _mm256_set1_ps(a);
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vdup<SIMD<double, 4>>(double a)
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{
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SIMD<double, 4> tmp;
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tmp.m = _mm256_set1_pd(a);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vdup<SIMD<int8_t, 32>>(int8_t a)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_set1_epi8(a);
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vdup<SIMD<int16_t, 16>>(int16_t a)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_set1_epi16(a);
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return tmp;
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}
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template <>
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inline SIMD<int32_t, 8> vdup<SIMD<int32_t, 8>>(int32_t a)
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{
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SIMD<int32_t, 8> tmp;
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tmp.m = _mm256_set1_epi32(a);
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return tmp;
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}
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template <>
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inline SIMD<int64_t, 4> vdup<SIMD<int64_t, 4>>(int64_t a)
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{
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SIMD<int64_t, 4> tmp;
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tmp.m = _mm256_set1_epi64x(a);
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return tmp;
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}
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template <>
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inline SIMD<float, 8> vzero()
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{
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SIMD<float, 8> tmp;
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tmp.m = _mm256_setzero_ps();
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vzero()
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{
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SIMD<double, 4> tmp;
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tmp.m = _mm256_setzero_pd();
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vzero()
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_setzero_si256();
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vzero()
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_setzero_si256();
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return tmp;
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}
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template <>
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inline SIMD<int32_t, 8> vzero()
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{
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SIMD<int32_t, 8> tmp;
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tmp.m = _mm256_setzero_si256();
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return tmp;
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}
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template <>
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inline SIMD<int64_t, 4> vzero()
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{
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SIMD<int64_t, 4> tmp;
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tmp.m = _mm256_setzero_si256();
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return tmp;
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}
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template <>
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inline SIMD<float, 8> vadd(SIMD<float, 8> a, SIMD<float, 8> b)
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{
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SIMD<float, 8> tmp;
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tmp.m = _mm256_add_ps(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vadd(SIMD<double, 4> a, SIMD<double, 4> b)
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{
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SIMD<double, 4> tmp;
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tmp.m = _mm256_add_pd(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vadd(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_add_epi8(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vadd(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_add_epi16(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int32_t, 8> vadd(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
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{
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SIMD<int32_t, 8> tmp;
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tmp.m = _mm256_add_epi32(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int64_t, 4> vadd(SIMD<int64_t, 4> a, SIMD<int64_t, 4> b)
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{
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SIMD<int64_t, 4> tmp;
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tmp.m = _mm256_add_epi64(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vqadd(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_adds_epi8(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vqadd(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_adds_epi16(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<float, 8> vsub(SIMD<float, 8> a, SIMD<float, 8> b)
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{
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SIMD<float, 8> tmp;
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tmp.m = _mm256_sub_ps(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vsub(SIMD<double, 4> a, SIMD<double, 4> b)
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{
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SIMD<double, 4> tmp;
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tmp.m = _mm256_sub_pd(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vsub(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_sub_epi8(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vsub(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_sub_epi16(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int32_t, 8> vsub(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
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{
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SIMD<int32_t, 8> tmp;
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tmp.m = _mm256_sub_epi32(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int64_t, 4> vsub(SIMD<int64_t, 4> a, SIMD<int64_t, 4> b)
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{
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SIMD<int64_t, 4> tmp;
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tmp.m = _mm256_sub_epi64(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vqsub(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
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{
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SIMD<int8_t, 32> tmp;
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tmp.m = _mm256_subs_epi8(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<int16_t, 16> vqsub(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
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{
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SIMD<int16_t, 16> tmp;
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tmp.m = _mm256_subs_epi16(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<uint8_t, 32> vqsub(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b)
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{
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SIMD<uint8_t, 32> tmp;
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tmp.m = _mm256_subs_epu8(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<uint16_t, 16> vqsub(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b)
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{
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SIMD<uint16_t, 16> tmp;
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tmp.m = _mm256_subs_epu16(a.m, b.m);
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return tmp;
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}
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template <>
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inline SIMD<float, 8> vabs(SIMD<float, 8> a)
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{
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SIMD<float, 8> tmp;
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tmp.m = _mm256_andnot_ps(_mm256_set1_ps(-0.f), a.m);
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return tmp;
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}
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template <>
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inline SIMD<double, 4> vabs(SIMD<double, 4> a)
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{
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SIMD<double, 4> tmp;
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tmp.m = _mm256_andnot_pd(_mm256_set1_pd(-0.), a.m);
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return tmp;
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}
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template <>
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inline SIMD<int8_t, 32> vqabs(SIMD<int8_t, 32> a)
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{
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SIMD<int8_t, 32> tmp;
|
||||
tmp.m = _mm256_abs_epi8(_mm256_max_epi8(a.m, _mm256_set1_epi8(-INT8_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 16> vqabs(SIMD<int16_t, 16> a)
|
||||
{
|
||||
SIMD<int16_t, 16> tmp;
|
||||
tmp.m = _mm256_abs_epi16(_mm256_max_epi16(a.m, _mm256_set1_epi16(-INT16_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 8> vqabs(SIMD<int32_t, 8> a)
|
||||
{
|
||||
SIMD<int32_t, 8> tmp;
|
||||
tmp.m = _mm256_abs_epi32(_mm256_max_epi32(a.m, _mm256_set1_epi32(-INT32_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 8> vsign(SIMD<float, 8> a, SIMD<float, 8> b)
|
||||
{
|
||||
SIMD<float, 8> tmp;
|
||||
tmp.m = _mm256_andnot_ps(
|
||||
_mm256_cmp_ps(b.m, _mm256_setzero_ps(), _CMP_EQ_OQ),
|
||||
_mm256_xor_ps(a.m, _mm256_and_ps(_mm256_set1_ps(-0.f), b.m)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 4> vsign(SIMD<double, 4> a, SIMD<double, 4> b)
|
||||
{
|
||||
SIMD<double, 4> tmp;
|
||||
tmp.m = _mm256_andnot_pd(
|
||||
_mm256_cmp_pd(b.m, _mm256_setzero_pd(), _CMP_EQ_OQ),
|
||||
_mm256_xor_pd(a.m, _mm256_and_pd(_mm256_set1_pd(-0.), b.m)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 32> vsign(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
|
||||
{
|
||||
SIMD<int8_t, 32> tmp;
|
||||
tmp.m = _mm256_sign_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 16> vsign(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
|
||||
{
|
||||
SIMD<int16_t, 16> tmp;
|
||||
tmp.m = _mm256_sign_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 8> vsign(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
|
||||
{
|
||||
SIMD<int32_t, 8> tmp;
|
||||
tmp.m = _mm256_sign_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vorr(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_or_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vorr(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_or_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vorr(SIMD<uint32_t, 8> a, SIMD<uint32_t, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_or_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vorr(SIMD<uint64_t, 4> a, SIMD<uint64_t, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_or_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vand(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_and_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vand(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_and_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vand(SIMD<uint32_t, 8> a, SIMD<uint32_t, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_and_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vand(SIMD<uint64_t, 4> a, SIMD<uint64_t, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_and_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> veor(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_xor_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> veor(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_xor_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> veor(SIMD<uint32_t, 8> a, SIMD<uint32_t, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_xor_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> veor(SIMD<uint64_t, 4> a, SIMD<uint64_t, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_xor_si256(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vbic(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_andnot_si256(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vbic(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_andnot_si256(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vbic(SIMD<uint32_t, 8> a, SIMD<uint32_t, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_andnot_si256(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vbic(SIMD<uint64_t, 4> a, SIMD<uint64_t, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_andnot_si256(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vbsl(SIMD<uint8_t, 32> a, SIMD<uint8_t, 32> b, SIMD<uint8_t, 32> c)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_or_si256(_mm256_and_si256(a.m, b.m), _mm256_andnot_si256(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vbsl(SIMD<uint16_t, 16> a, SIMD<uint16_t, 16> b, SIMD<uint16_t, 16> c)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_or_si256(_mm256_and_si256(a.m, b.m), _mm256_andnot_si256(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vbsl(SIMD<uint32_t, 8> a, SIMD<uint32_t, 8> b, SIMD<uint32_t, 8> c)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_or_si256(_mm256_and_si256(a.m, b.m), _mm256_andnot_si256(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vbsl(SIMD<uint64_t, 4> a, SIMD<uint64_t, 4> b, SIMD<uint64_t, 4> c)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_or_si256(_mm256_and_si256(a.m, b.m), _mm256_andnot_si256(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vceqz(SIMD<float, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_ps(a.m, _mm256_setzero_ps(), _CMP_EQ_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vceqz(SIMD<double, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_pd(a.m, _mm256_setzero_pd(), _CMP_EQ_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vceqz(SIMD<int8_t, 32> a)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi8(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vceqz(SIMD<int16_t, 16> a)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi16(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vceqz(SIMD<int32_t, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi32(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vceqz(SIMD<int64_t, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi64(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vceq(SIMD<float, 8> a, SIMD<float, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_ps(a.m, b.m, _CMP_EQ_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vceq(SIMD<double, 4> a, SIMD<double, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_pd(a.m, b.m, _CMP_EQ_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vceq(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vceq(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vceq(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vceq(SIMD<int64_t, 4> a, SIMD<int64_t, 4> b)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_cmpeq_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vcgtz(SIMD<float, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_ps(a.m, _mm256_setzero_ps(), _CMP_GT_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vcgtz(SIMD<double, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_pd(a.m, _mm256_setzero_pd(), _CMP_GT_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vcgtz(SIMD<int8_t, 32> a)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi8(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vcgtz(SIMD<int16_t, 16> a)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi16(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vcgtz(SIMD<int32_t, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi32(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vcgtz(SIMD<int64_t, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi64(a.m, _mm256_setzero_si256());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vcltz(SIMD<float, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_ps(a.m, _mm256_setzero_ps(), _CMP_LT_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vcltz(SIMD<double, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = (__m256i)_mm256_cmp_pd(a.m, _mm256_setzero_pd(), _CMP_LT_OQ);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 32> vcltz(SIMD<int8_t, 32> a)
|
||||
{
|
||||
SIMD<uint8_t, 32> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi8(_mm256_setzero_si256(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 16> vcltz(SIMD<int16_t, 16> a)
|
||||
{
|
||||
SIMD<uint16_t, 16> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi16(_mm256_setzero_si256(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 8> vcltz(SIMD<int32_t, 8> a)
|
||||
{
|
||||
SIMD<uint32_t, 8> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi32(_mm256_setzero_si256(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 4> vcltz(SIMD<int64_t, 4> a)
|
||||
{
|
||||
SIMD<uint64_t, 4> tmp;
|
||||
tmp.m = _mm256_cmpgt_epi64(_mm256_setzero_si256(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 8> vmin(SIMD<float, 8> a, SIMD<float, 8> b)
|
||||
{
|
||||
SIMD<float, 8> tmp;
|
||||
tmp.m = _mm256_min_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 4> vmin(SIMD<double, 4> a, SIMD<double, 4> b)
|
||||
{
|
||||
SIMD<double, 4> tmp;
|
||||
tmp.m = _mm256_min_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 32> vmin(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
|
||||
{
|
||||
SIMD<int8_t, 32> tmp;
|
||||
tmp.m = _mm256_min_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 16> vmin(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
|
||||
{
|
||||
SIMD<int16_t, 16> tmp;
|
||||
tmp.m = _mm256_min_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 8> vmin(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
|
||||
{
|
||||
SIMD<int32_t, 8> tmp;
|
||||
tmp.m = _mm256_min_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 4> vmin(SIMD<int64_t, 4> a, SIMD<int64_t, 4> b)
|
||||
{
|
||||
SIMD<int64_t, 4> tmp;
|
||||
tmp.m = _mm256_min_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 8> vmax(SIMD<float, 8> a, SIMD<float, 8> b)
|
||||
{
|
||||
SIMD<float, 8> tmp;
|
||||
tmp.m = _mm256_max_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 4> vmax(SIMD<double, 4> a, SIMD<double, 4> b)
|
||||
{
|
||||
SIMD<double, 4> tmp;
|
||||
tmp.m = _mm256_max_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 32> vmax(SIMD<int8_t, 32> a, SIMD<int8_t, 32> b)
|
||||
{
|
||||
SIMD<int8_t, 32> tmp;
|
||||
tmp.m = _mm256_max_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 16> vmax(SIMD<int16_t, 16> a, SIMD<int16_t, 16> b)
|
||||
{
|
||||
SIMD<int16_t, 16> tmp;
|
||||
tmp.m = _mm256_max_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 8> vmax(SIMD<int32_t, 8> a, SIMD<int32_t, 8> b)
|
||||
{
|
||||
SIMD<int32_t, 8> tmp;
|
||||
tmp.m = _mm256_max_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 4> vmax(SIMD<int64_t, 4> a, SIMD<int64_t, 4> b)
|
||||
{
|
||||
SIMD<int64_t, 4> tmp;
|
||||
tmp.m = _mm256_max_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
#endif
|
||||
843
neon.hh
Normal file
843
neon.hh
Normal file
|
|
@ -0,0 +1,843 @@
|
|||
/*
|
||||
ARM NEON acceleration
|
||||
|
||||
Copyright 2018 Ahmet Inan <inan@aicodix.de>
|
||||
*/
|
||||
|
||||
#ifndef NEON_HH
|
||||
#define NEON_HH
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
template <>
|
||||
union SIMD<float, 4>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef float value_type;
|
||||
typedef uint32_t uint_type;
|
||||
float32x4_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int8_t, 16>
|
||||
{
|
||||
static const int SIZE = 16;
|
||||
typedef int8_t value_type;
|
||||
typedef uint8_t uint_type;
|
||||
int8x16_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int16_t, 8>
|
||||
{
|
||||
static const int SIZE = 8;
|
||||
typedef int16_t value_type;
|
||||
typedef uint16_t uint_type;
|
||||
int16x8_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int32_t, 4>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef int32_t value_type;
|
||||
typedef uint32_t uint_type;
|
||||
int32x4_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int64_t, 2>
|
||||
{
|
||||
static const int SIZE = 2;
|
||||
typedef int64_t value_type;
|
||||
typedef uint64_t uint_type;
|
||||
int64x2_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint8_t, 16>
|
||||
{
|
||||
static const int SIZE = 16;
|
||||
typedef uint8_t value_type;
|
||||
typedef uint8_t uint_type;
|
||||
uint8x16_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint16_t, 8>
|
||||
{
|
||||
static const int SIZE = 8;
|
||||
typedef uint16_t value_type;
|
||||
typedef uint16_t uint_type;
|
||||
uint16x8_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint32_t, 4>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef uint32_t value_type;
|
||||
typedef uint32_t uint_type;
|
||||
uint32x4_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint64_t, 2>
|
||||
{
|
||||
static const int SIZE = 2;
|
||||
typedef uint64_t value_type;
|
||||
typedef uint64_t uint_type;
|
||||
uint64x2_t m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vreinterpret(SIMD<uint32_t, 4> a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = (float32x4_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vreinterpret(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (uint32x4_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vreinterpret(SIMD<uint8_t, 16> a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = (int8x16_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vreinterpret(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = (uint8x16_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vreinterpret(SIMD<uint16_t, 8> a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = (int16x8_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vreinterpret(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = (uint16x8_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vreinterpret(SIMD<uint32_t, 4> a)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = (int32x4_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vreinterpret(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (uint32x4_t)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vdup(float a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vdupq_n_f32(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vdup(int8_t a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vdupq_n_s8(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vdup(int16_t a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vdupq_n_s16(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vdup(int32_t a)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = vdupq_n_s32(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vdup(int64_t a)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = vdupq_n_s64(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vdup(uint8_t a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vdupq_n_u8(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vdup(uint16_t a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vdupq_n_u16(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vdup(uint32_t a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vdupq_n_u32(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vdup(uint64_t a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = vdupq_n_u64(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vzero()
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = (float32x4_t)veorq_u32((uint32x4_t)tmp.m, (uint32x4_t)tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vzero()
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = veorq_s8(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vzero()
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = veorq_s16(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vzero()
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = veorq_s32(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vzero()
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = veorq_s64(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vzero()
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = veorq_u8(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vzero()
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = veorq_u16(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vzero()
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = veorq_u32(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vzero()
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = veorq_u64(tmp.m, tmp.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vadd(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vaddq_f32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vadd(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vaddq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vadd(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vaddq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vadd(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = vaddq_s32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vadd(SIMD<int64_t, 2> a, SIMD<int64_t, 2> b)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = vaddq_s64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqadd(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vqaddq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqadd(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vqaddq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vsub(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vsubq_f32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vsub(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vsubq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vsub(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vsubq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vsub(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = vsubq_s32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vsub(SIMD<int64_t, 2> a, SIMD<int64_t, 2> b)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = vsubq_s64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqsub(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vqsubq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqsub(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vqsubq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vqsub(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vqsubq_u8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vqsub(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vqsubq_u16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vabs(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vabsq_f32(a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqabs(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vqabsq_s8(a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqabs(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vqabsq_s16(a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vsign(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = (float32x4_t)vbicq_u32(
|
||||
veorq_u32((uint32x4_t)a.m, vandq_u32((uint32x4_t)vdupq_n_f32(-0.f), (uint32x4_t)b.m)),
|
||||
vceqq_f32(b.m, vdupq_n_f32(0.f)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vsign(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = (int8x16_t)vorrq_u8(
|
||||
vandq_u8(vcgtq_s8(vdupq_n_s8(0), b.m), (uint8x16_t)vnegq_s8(a.m)),
|
||||
vandq_u8(vcgtq_s8(b.m, vdupq_n_s8(0)), (uint8x16_t)a.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vorr(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vorrq_u8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vorr(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vorrq_u16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vorr(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vorrq_u32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vorr(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = vorrq_u64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vand(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vandq_u8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vand(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vandq_u16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vand(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vandq_u32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vand(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = vandq_u64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> veor(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = veorq_u8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> veor(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = veorq_u16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> veor(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = veorq_u32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> veor(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = veorq_u64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vbic(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vbicq_u8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vbic(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vbicq_u16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vbic(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vbicq_u32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vbic(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = vbicq_u64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vbsl(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b, SIMD<uint8_t, 16> c)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vbslq_u8(a.m, b.m, c.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vbsl(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b, SIMD<uint16_t, 8> c)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vbslq_u16(a.m, b.m, c.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vbsl(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b, SIMD<uint32_t, 4> c)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vbslq_u32(a.m, b.m, c.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vbsl(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b, SIMD<uint64_t, 2> c)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = vbslq_u64(a.m, b.m, c.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceqz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vceqq_f32(a.m, vdupq_n_f32(0.f));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vceqz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vceqq_s8(a.m, vdupq_n_s8(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vceqz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vceqq_s16(a.m, vdupq_n_s16(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceqz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vceqq_s32(a.m, vdupq_n_s32(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceq(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vceqq_f32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vceq(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vceqq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vceq(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vceqq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceq(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vceqq_s32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcgtz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vcgtq_f32(a.m, vdupq_n_f32(0.f));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vcgtz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vcgtq_s8(a.m, vdupq_n_s8(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vcgtz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vcgtq_s16(a.m, vdupq_n_s16(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcgtz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vcgtq_s32(a.m, vdupq_n_s32(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcltz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vcltq_f32(a.m, vdupq_n_f32(0.f));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vcltz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = vcltq_s8(a.m, vdupq_n_s8(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vcltz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = vcltq_s16(a.m, vdupq_n_s16(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcltz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = vcltq_s32(a.m, vdupq_n_s32(0));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vmin(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vminq_f32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vmin(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vminq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vmin(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vminq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vmin(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = vminq_s32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vmax(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = vmaxq_f32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vmax(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = vmaxq_s8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vmax(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = vmaxq_s16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vmax(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = vmaxq_s32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
#endif
|
||||
975
sse4_1.hh
Normal file
975
sse4_1.hh
Normal file
|
|
@ -0,0 +1,975 @@
|
|||
/*
|
||||
Intel SSE4.1 acceleration
|
||||
|
||||
Copyright 2018 Ahmet Inan <inan@aicodix.de>
|
||||
*/
|
||||
|
||||
#ifndef SSE4_1_HH
|
||||
#define SSE4_1_HH
|
||||
|
||||
#include <smmintrin.h>
|
||||
|
||||
template <>
|
||||
union SIMD<float, 4>
|
||||
{
|
||||
static const int SIZE = 8;
|
||||
typedef float value_type;
|
||||
typedef uint32_t uint_type;
|
||||
__m128 m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<double, 2>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef double value_type;
|
||||
typedef uint64_t uint_type;
|
||||
__m128d m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int8_t, 16>
|
||||
{
|
||||
static const int SIZE = 32;
|
||||
typedef int8_t value_type;
|
||||
typedef uint8_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int16_t, 8>
|
||||
{
|
||||
static const int SIZE = 16;
|
||||
typedef int16_t value_type;
|
||||
typedef uint16_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int32_t, 4>
|
||||
{
|
||||
static const int SIZE = 8;
|
||||
typedef int32_t value_type;
|
||||
typedef uint32_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<int64_t, 2>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef int64_t value_type;
|
||||
typedef uint64_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint8_t, 16>
|
||||
{
|
||||
static const int SIZE = 32;
|
||||
typedef uint8_t value_type;
|
||||
typedef uint8_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint16_t, 8>
|
||||
{
|
||||
static const int SIZE = 16;
|
||||
typedef uint16_t value_type;
|
||||
typedef uint16_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint32_t, 4>
|
||||
{
|
||||
static const int SIZE = 8;
|
||||
typedef uint32_t value_type;
|
||||
typedef uint32_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
union SIMD<uint64_t, 2>
|
||||
{
|
||||
static const int SIZE = 4;
|
||||
typedef uint64_t value_type;
|
||||
typedef uint64_t uint_type;
|
||||
__m128i m;
|
||||
value_type v[SIZE];
|
||||
uint_type u[SIZE];
|
||||
};
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vreinterpret(SIMD<uint32_t, 4> a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = (__m128)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vreinterpret(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vreinterpret(SIMD<uint64_t, 2> a)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = (__m128d)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vreinterpret(SIMD<double, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vreinterpret(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vreinterpret(SIMD<uint8_t, 16> a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vreinterpret(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vreinterpret(SIMD<uint16_t, 8> a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vreinterpret(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vreinterpret(SIMD<uint32_t, 4> a)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vreinterpret(SIMD<int64_t, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vreinterpret(SIMD<uint64_t, 2> a)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = (__m128i)a.m;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vdup<SIMD<float, 4>>(float a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_set1_ps(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vdup<SIMD<double, 2>>(double a)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_set1_pd(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vdup<SIMD<int8_t, 16>>(int8_t a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_set1_epi8(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vdup<SIMD<int16_t, 8>>(int16_t a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_set1_epi16(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vdup<SIMD<int32_t, 4>>(int32_t a)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_set1_epi32(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vdup<SIMD<int64_t, 2>>(int64_t a)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = _mm_set1_epi64x(a);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vzero()
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_setzero_ps();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vzero()
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_setzero_pd();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vzero()
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_setzero_si128();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vzero()
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_setzero_si128();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vzero()
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_setzero_si128();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vzero()
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = _mm_setzero_si128();
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vadd(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_add_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vadd(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_add_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vadd(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_add_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vadd(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_add_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vadd(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_add_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vadd(SIMD<int64_t, 2> a, SIMD<int64_t, 2> b)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = _mm_add_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqadd(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_adds_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqadd(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_adds_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vsub(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_sub_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vsub(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_sub_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vsub(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_sub_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vsub(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_sub_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vsub(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_sub_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int64_t, 2> vsub(SIMD<int64_t, 2> a, SIMD<int64_t, 2> b)
|
||||
{
|
||||
SIMD<int64_t, 2> tmp;
|
||||
tmp.m = _mm_sub_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqsub(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_subs_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqsub(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_subs_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vqsub(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_subs_epu8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vqsub(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_subs_epu16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vabs(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_andnot_ps(_mm_set1_ps(-0.f), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vabs(SIMD<double, 2> a)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_andnot_pd(_mm_set1_pd(-0.), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vqabs(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_abs_epi8(_mm_max_epi8(a.m, _mm_set1_epi8(-INT8_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vqabs(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_abs_epi16(_mm_max_epi16(a.m, _mm_set1_epi16(-INT16_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vqabs(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_abs_epi32(_mm_max_epi32(a.m, _mm_set1_epi32(-INT32_MAX)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vsign(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_andnot_ps(
|
||||
_mm_cmpeq_ps(b.m, _mm_setzero_ps()),
|
||||
_mm_xor_ps(a.m, _mm_and_ps(_mm_set1_ps(-0.f), b.m)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vsign(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_andnot_pd(
|
||||
_mm_cmpeq_pd(b.m, _mm_setzero_pd()),
|
||||
_mm_xor_pd(a.m, _mm_and_pd(_mm_set1_pd(-0.), b.m)));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vsign(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_sign_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vsign(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_sign_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vsign(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_sign_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vorr(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_or_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vorr(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_or_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vorr(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_or_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vorr(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_or_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vand(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_and_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vand(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_and_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vand(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_and_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vand(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_and_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> veor(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_xor_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> veor(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_xor_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> veor(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_xor_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> veor(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_xor_si128(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vbic(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_andnot_si128(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vbic(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_andnot_si128(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vbic(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_andnot_si128(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vbic(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_andnot_si128(b.m, a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vbsl(SIMD<uint8_t, 16> a, SIMD<uint8_t, 16> b, SIMD<uint8_t, 16> c)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_or_si128(_mm_and_si128(a.m, b.m), _mm_andnot_si128(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vbsl(SIMD<uint16_t, 8> a, SIMD<uint16_t, 8> b, SIMD<uint16_t, 8> c)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_or_si128(_mm_and_si128(a.m, b.m), _mm_andnot_si128(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vbsl(SIMD<uint32_t, 4> a, SIMD<uint32_t, 4> b, SIMD<uint32_t, 4> c)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_or_si128(_mm_and_si128(a.m, b.m), _mm_andnot_si128(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vbsl(SIMD<uint64_t, 2> a, SIMD<uint64_t, 2> b, SIMD<uint64_t, 2> c)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_or_si128(_mm_and_si128(a.m, b.m), _mm_andnot_si128(a.m, c.m));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceqz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpeq_ps(a.m, _mm_setzero_ps());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vceqz(SIMD<double, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpeq_pd(a.m, _mm_setzero_pd());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vceqz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_cmpeq_epi8(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vceqz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_cmpeq_epi16(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceqz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_cmpeq_epi32(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vceqz(SIMD<int64_t, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_cmpeq_epi64(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceq(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpeq_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vceq(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpeq_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vceq(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_cmpeq_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vceq(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_cmpeq_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vceq(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_cmpeq_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vceq(SIMD<int64_t, 2> a, SIMD<int64_t, 2> b)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_cmpeq_epi64(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcgtz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpgt_ps(a.m, _mm_setzero_ps());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vcgtz(SIMD<double, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)_mm_cmpgt_pd(a.m, _mm_setzero_pd());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vcgtz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_cmpgt_epi8(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vcgtz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_cmpgt_epi16(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcgtz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_cmpgt_epi32(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vcgtz(SIMD<int64_t, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_cmpgt_epi64(a.m, _mm_setzero_si128());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcltz(SIMD<float, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = (__m128i)_mm_cmplt_ps(a.m, _mm_setzero_ps());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vcltz(SIMD<double, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = (__m128i)_mm_cmplt_pd(a.m, _mm_setzero_pd());
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint8_t, 16> vcltz(SIMD<int8_t, 16> a)
|
||||
{
|
||||
SIMD<uint8_t, 16> tmp;
|
||||
tmp.m = _mm_cmpgt_epi8(_mm_setzero_si128(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint16_t, 8> vcltz(SIMD<int16_t, 8> a)
|
||||
{
|
||||
SIMD<uint16_t, 8> tmp;
|
||||
tmp.m = _mm_cmpgt_epi16(_mm_setzero_si128(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint32_t, 4> vcltz(SIMD<int32_t, 4> a)
|
||||
{
|
||||
SIMD<uint32_t, 4> tmp;
|
||||
tmp.m = _mm_cmpgt_epi32(_mm_setzero_si128(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<uint64_t, 2> vcltz(SIMD<int64_t, 2> a)
|
||||
{
|
||||
SIMD<uint64_t, 2> tmp;
|
||||
tmp.m = _mm_cmpgt_epi64(_mm_setzero_si128(), a.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vmin(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_min_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vmin(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_min_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vmin(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_min_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vmin(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_min_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vmin(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_min_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<float, 4> vmax(SIMD<float, 4> a, SIMD<float, 4> b)
|
||||
{
|
||||
SIMD<float, 4> tmp;
|
||||
tmp.m = _mm_max_ps(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<double, 2> vmax(SIMD<double, 2> a, SIMD<double, 2> b)
|
||||
{
|
||||
SIMD<double, 2> tmp;
|
||||
tmp.m = _mm_max_pd(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int8_t, 16> vmax(SIMD<int8_t, 16> a, SIMD<int8_t, 16> b)
|
||||
{
|
||||
SIMD<int8_t, 16> tmp;
|
||||
tmp.m = _mm_max_epi8(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int16_t, 8> vmax(SIMD<int16_t, 8> a, SIMD<int16_t, 8> b)
|
||||
{
|
||||
SIMD<int16_t, 8> tmp;
|
||||
tmp.m = _mm_max_epi16(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <>
|
||||
inline SIMD<int32_t, 4> vmax(SIMD<int32_t, 4> a, SIMD<int32_t, 4> b)
|
||||
{
|
||||
SIMD<int32_t, 4> tmp;
|
||||
tmp.m = _mm_max_epi32(a.m, b.m);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue