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removed negz constants for consistency
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parent
992c83933d
commit
56903fc707
6 changed files with 16 additions and 24 deletions
10
avx2.hh
10
avx2.hh
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@ -602,10 +602,9 @@ template <>
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inline SIMD<float, 8> vcopysign(SIMD<float, 8> a, SIMD<float, 8> b)
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{
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SIMD<float, 8> tmp;
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__m256 negz = _mm256_set1_ps(-0.f);
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tmp.m = _mm256_or_ps(
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_mm256_andnot_ps(negz, a.m),
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_mm256_and_ps(negz, b.m));
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_mm256_andnot_ps(_mm256_set1_ps(-0.f), a.m),
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_mm256_and_ps(_mm256_set1_ps(-0.f), b.m));
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return tmp;
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}
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@ -613,10 +612,9 @@ template <>
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inline SIMD<double, 4> vcopysign(SIMD<double, 4> a, SIMD<double, 4> b)
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{
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SIMD<double, 4> tmp;
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__m256d negz = _mm256_set1_pd(-0.);
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tmp.m = _mm256_or_pd(
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_mm256_andnot_pd(negz, a.m),
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_mm256_and_pd(negz, b.m));
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_mm256_andnot_pd(_mm256_set1_pd(-0.), a.m),
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_mm256_and_pd(_mm256_set1_pd(-0.), b.m));
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return tmp;
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}
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5
neon.hh
5
neon.hh
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@ -526,10 +526,9 @@ template <>
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inline SIMD<float, 4> vcopysign(SIMD<float, 4> a, SIMD<float, 4> b)
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{
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SIMD<float, 4> tmp;
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uint32x4_t negz = (uint32x4_t)vdupq_n_f32(-0.f);
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tmp.m = (float32x4_t)vorrq_u32(
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vbicq_u32((uint32x4_t)a.m, negz),
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vandq_u32((uint32x4_t)b.m, negz));
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vbicq_u32((uint32x4_t)a.m, (uint32x4_t)vdupq_n_f32(-0.f)),
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vandq_u32((uint32x4_t)b.m, (uint32x4_t)vdupq_n_f32(-0.f)));
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return tmp;
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}
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@ -577,11 +577,10 @@ template <>
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inline SIMD<float, 8> vcopysign(SIMD<float, 8> a, SIMD<float, 8> b)
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{
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SIMD<float, 8> tmp;
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uint32x4_t negz = (uint32x4_t)vdupq_n_f32(-0.f);
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for (int i = 0; i < 2; ++i)
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tmp.m[i] = (float32x4_t)vorrq_u32(
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vbicq_u32((uint32x4_t)a.m[i], negz),
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vandq_u32((uint32x4_t)b.m[i], negz));
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vbicq_u32((uint32x4_t)a.m[i], (uint32x4_t)vdupq_n_f32(-0.f)),
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vandq_u32((uint32x4_t)b.m[i], (uint32x4_t)vdupq_n_f32(-0.f)));
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return tmp;
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}
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@ -577,11 +577,10 @@ template <>
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inline SIMD<float, 16> vcopysign(SIMD<float, 16> a, SIMD<float, 16> b)
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{
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SIMD<float, 16> tmp;
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uint32x4_t negz = (uint32x4_t)vdupq_n_f32(-0.f);
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for (int i = 0; i < 4; ++i)
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tmp.m[i] = (float32x4_t)vorrq_u32(
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vbicq_u32((uint32x4_t)a.m[i], negz),
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vandq_u32((uint32x4_t)b.m[i], negz));
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vbicq_u32((uint32x4_t)a.m[i], (uint32x4_t)vdupq_n_f32(-0.f)),
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vandq_u32((uint32x4_t)b.m[i], (uint32x4_t)vdupq_n_f32(-0.f)));
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return tmp;
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}
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@ -577,11 +577,10 @@ template <>
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inline SIMD<float, 12> vcopysign(SIMD<float, 12> a, SIMD<float, 12> b)
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{
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SIMD<float, 12> tmp;
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uint32x4_t negz = (uint32x4_t)vdupq_n_f32(-0.f);
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for (int i = 0; i < 3; ++i)
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tmp.m[i] = (float32x4_t)vorrq_u32(
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vbicq_u32((uint32x4_t)a.m[i], negz),
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vandq_u32((uint32x4_t)b.m[i], negz));
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vbicq_u32((uint32x4_t)a.m[i], (uint32x4_t)vdupq_n_f32(-0.f)),
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vandq_u32((uint32x4_t)b.m[i], (uint32x4_t)vdupq_n_f32(-0.f)));
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return tmp;
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}
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10
sse4_1.hh
10
sse4_1.hh
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@ -602,10 +602,9 @@ template <>
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inline SIMD<float, 4> vcopysign(SIMD<float, 4> a, SIMD<float, 4> b)
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{
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SIMD<float, 4> tmp;
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__m128 negz = _mm_set1_ps(-0.f);
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tmp.m = _mm_or_ps(
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_mm_andnot_ps(negz, a.m),
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_mm_and_ps(negz, b.m));
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_mm_andnot_ps(_mm_set1_ps(-0.f), a.m),
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_mm_and_ps(_mm_set1_ps(-0.f), b.m));
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return tmp;
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}
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@ -613,10 +612,9 @@ template <>
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inline SIMD<double, 2> vcopysign(SIMD<double, 2> a, SIMD<double, 2> b)
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{
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SIMD<double, 2> tmp;
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__m128d negz = _mm_set1_pd(-0.);
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tmp.m = _mm_or_pd(
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_mm_andnot_pd(negz, a.m),
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_mm_and_pd(negz, b.m));
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_mm_andnot_pd(_mm_set1_pd(-0.), a.m),
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_mm_and_pd(_mm_set1_pd(-0.), b.m));
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return tmp;
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}
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